1. Field of the Invention
The present invention relates to a cell switch which is used in ATM communication systems, and particularly to a cell switch which can be operated efficiently in nonsynchronous routing networks.
2. Description of the Prior Art
As a conventional information transfer mode used in telephone networks, there is a so-called asynchronous transfer mode (ATM) in which the information transfer function of the communication network can be optionally used by communication terminals. According to the ATM, each information is transferred as a short packet with a fixed length called a cell, and each communication terminal can optionally transfer the cell to the communication network, that is, each communication terminal can optionally use the information transfer function of the network.
To construct the ATM communication network, it is necessary to realize a function or a cell switch system for outputting cells to be transferred from a plurality of input communication routes to desired communication routes respectively. In this case, since the information transfer function of the communication network is used by a plurality of communication terminals, a so-called blocking state in which a plurality of cells are given to the same output communication route at the same time is generated. However, such blocking is usually avoided by transferring one of the plurality of cells to the output communication route and storing the other cells temporarily in a buffer.
As the method of avoiding the blocking, various methods are now studied. Particularly, since the blocking avoiding method depends much on the switching ability, it is desired to develop a cell switch system which can effectively avoid the blocking.
Among cell switch systems having been proposed so far, the cell switch system based on the so-called dispersion-collision avoiding input buffer method reported by the inventors, "Comparison Study of The ATM Switch Architecture" (Electronic Information Communication Society Research Report. Information Network Study Meeting IN88-119, pp13-17, 1989) is characterized in that a buffer is three-dimensionally assigned to a position from which the blocking is generated so as to avoid the blocking. This cell switch system generally comprises a switch network known as a multi-stage self routing network with buffers. In more detail, the multi-stage routing network with buffers means a switch network where a buffer is provided in each 2-input-2-output unit switch (hereinafter simply called unit switch) so as to avoid the blocking. Moreover, as is well known, the multi-stage self routing network is constructed by connecting a plurality of unit switches, and it can introduce cells inputted from input communication routes to desired output communication routes, respectively, by switching the transfer route of each cell in accordance with a bit value corresponding to a predetermined position of the cell.
In the conventional cell switch system based on this multi-stage self routing network with buffers, all of the unit switches of the network are operated in synchronism with one another (hereinafter, this system is called a synchronous-type system). However, in such a synchronous-type system, the time required for transferring 1 bit of each cell between unit switches (hereinafter called switch-to-switch cell transfer delay time) determines the maximum frequency Ftrns of a clock signal for transferring the cell. FIGS.1 and 2 are a diagram and a timing chart to explain the switch-to-switch cell transfer delay time when the i-th bit of a cell is transferred from a unit switch (x) to the next unit switch (x+1) by the serial operation. Reference characters designated in the same drawings have the following meanings respectively.
CK: Cell transfer clock signal PA1 K(x): Cell transfer clock signal in the unit switch (x) PA1 CK(x+1): Cell transfer clock signal in the unit switch (x+1) PA1 Tstr: Time required for outputting data of a cell to a node D from rise of CK(x) PA1 Topb: Output buffer internal delay time PA1 Tlin: Cell transfer delay time PA1 Tipb: Input buffer internal delay time PA1 Tset: Set-up time of a data-type flip-flop (DFF) PA1 Ts(x, x+1): Skew (phase shift) between CK(x) and CK(x+1) PA1 Tcyc: Cycle of CK, CK(x), CK(x+1) PA1 Ftrns: Frequency of CK, CK(x), CK(x+1) PA1 Tstr=1 ns PA1 Topb=3 ns PA1 Tlin=1 ns PA1 Tipb=3 ns PA1 Tsct=1 ns PA1 Ts(x, x+1)=1 ns PA1 Tdly=Tcyc=11 ns
If the above-mentioned switch-to-switch cell transfer delay time is now designated by Tdly, the delay time Tdly can be expressed as follows based on the timing chart given in FIG. 2. ##EQU1##
Namely, Tdly or Tcyc is obtained as follows under the following conditions:
As the result, the maximum transfer frequency Ftrns on the serial transfer operation becomes as follows: EQU Ftrns=1/Tcyc=90.9 Mbps.
On the other hand, both Tlin and Ts(x, x+1) become large in FIG. 2 as the scale of the cell switch system becomes large, for example, as the number of input-output channels becomes 256 to 1024. Therefore, Ftrns becomes small with enlargement of the switching scale.
According to the conventional synchronous-type system, It becomes difficult to make the system large in scale while keeping the cell transfer frequency at a suitable value.
The cell switch system disclosed by the inventors in Japanese Patent Application No.135819/1989 is so constructed as to realize a function (hereinafter called simultaneous cell Input-output function) for executing input and output of cells at the same time by division transfer by unit switches, in order to reduce the time (hereinafter called cell delay time) from input to output of the cells. However, according to the synchronous-type system, it is not possible to execute the simultaneous cell input-output function by a specific unit switch preferentially to the other unit switches, because the input and output operation of cells are executed at the same time by all of the unit switches. Therefore, in the cell switch system of this case, there still remains a problem in that the simultaneous cell input-output function can not be utilized effectively.
Like this, the conventional technology for realizing the simultaneous cell input-output function depends only on the synchronous routing switch network with no cell storing means (buffer). However, in case of asynchronous routing networks, a problem is that each unit switch can not output cells to the following unit switch until the preparation for receiving the cells from the former switch is completed in the latter switch. Therefore, it is very difficult to apply the asynchronous routing network to the conventional method of realizing the simultaneous cell input-output function.
Generally, in digital information processing systems employing the asynchronous-type system, the hardware must be complicated to control the respective asynchronous function blocks to be in synchronous relation to one another. Therefore, it becomes very difficult to design timing for the whole operation. Moreover, since it takes much time to establish the synchronism relation, the cell delay time is increased.
In the cell switch system based on the conventional multi-stage self routing network with buffers, each unit switch is not provided with means for stopping the generating of a clock signal for driving the cell input-output means when no input and output of cells are executed. Therefore, the power consumption is unnecessarily large.
As stated above, the following problems exist in the conventional cell switch system:
(1) it is very difficult to attempt to make the switch system large in size while keeping the cell transfer frequency at a desired value in the synchronous-type operation system,
(2) the simultaneous cell input-output function is not efficiently utilized because the unit switches always execute the input and output of cells at the same time in the synchronous operation system,
(3) it is not possible to apply the conventional method of realizing the simultaneous cell input-output function to the asynchronous-type routing switch network,
(4) asynchronous operation of the routing network requires complicated hardware and difficult timing design, and
(5) the unit switches constructing the network tend to unnecessarily and greatly increase the power consumption of the whole system.